This application claims priority to S.N. 99400555.1, filed in Europe on Mar. 8, 1999 (TI-27763EU) and S.N. 98402455.4, filed in Europe on Oct. 6, 1998 (TI-28433EU).
1. Field of the Invention
The present invention relates to digital microprocessors, and more particularly to instruction sets for digital microprocessors.
2. Background of the Invention
Microprocessors are general purpose processors which require high instruction throughputs in order to execute software running thereon, and can have a wide range of processing requirements depending on the particular software applications involved. Instruction sets for microprocessors-typically contain different instructions for accessing data from various storage locations, such as main memory, I/O, or registers.
Many different types of processors are known, of which microprocessors are but one example. For example, Digital Signal Processors (DSPs) are widely used, in particular for specific applications, such as mobile processing applications. DSPs are typically configured to optimize the performance of the applications concerned and to achieve this they employ more specialized execution units and instruction sets. Particularly in, but not exclusively, applications such as mobile telecommunications applications, it is desirable to provide ever increasing DSP performance while keeping power consumption as low as possible.
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims. The present invention is directed to improving the performance of processors, such as for example, but not exclusively, digital signal processors.
In accordance with a first aspect of the invention, there is provided a processor that is a programmable digital signal processor (DSP), offering both high code density and easy programming. Architecture and instruction set are optimized for low power consumption and high efficiency execution of DSP algorithms, such as for wireless telephones, as well as pure control tasks. The processor includes an instruction buffer unit operable to decode an instruction fetched from an instruction memory. The instruction may have a number of instruction formats. A data address generation unit is operable to calculate a first address of a first operand in response to a first instruction. The instruction buffer unit is further operable to decode a second instruction from the sequence of instructions in a combined manner while decoding the first instruction; such that the decoding of the first instruction is qualified by the second instruction. The processor has means for retrieving the first operand in response to the first address, means for manipulating the first operand, and means for providing an instruction address that identifies an instruction in the instruction stream to be decoded by the instruction buffer unit.
In accordance with another aspect of the present invention, the data address generation unit is operable to calculate a second address of a second operand instead of the first address in response to the second instruction.
In accordance with another aspect of the present invention, the first address of the first operand is in a memory address space, and the second address of the second operand is a memory mapped register.
In accordance with another aspect of the present invention, the first address of the first operand is in a memory address space, and the second address of the second operand is a peripheral device register.
In accordance with another aspect of the present invention, a method of operating a digital system is provided. A plurality of instructions are executed in an instruction pipeline of the processor core, wherein the instructions are fetched in response to a program counter from an instruction memory associated with the processor core, wherein the sequence of instructions are selected from an instruction set having a number of instruction formats. A first instruction from the sequence is decoded, wherein the first instruction has a first format selected from the plurality of instruction formats. A first data item is manipulated in a first manner in response to the step of decoding the first instruction. Later, a second instruction from the sequence is decoded, in this case the second instruction is identical to the first instruction. However, a qualifier instruction is decoded in a combined manner with the step of decoding the second instruction, such that the step of decoding the second instruction is qualified by the step of decoding the third instruction. A second data item is manipulated in response to the combined manner of decoding the second instruction and the qualifier instruction in a different manner than the step of manipulating the first data item.